The present invention relates generally to semiconductor memory devices. More particularly, the invention relates to phase change memory devices and methods of discharging a bitline in same.
Semiconductor memory devices may be generally classified as random access memory (RAM) and read only memory (ROM). ROM is a non-volatile memory that retains stored data in absence of applied power. Examples of ROM include programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), flash memory, etc. In contrast, RAM is a volatile memory that loses stored data when applied power is interrupted. Examples of RAM include dynamic RAM (DRAM), static RAM (SRAM), etc. RAM typically stores electrical charge indicative of a data value using a capacitor.
Besides the aforementioned memory devices, there are other types of semiconductor memory that replace the standard RAM capacitor with a non-volatile data storage element. Examples include the ferroelectric RAM (FRAM) which uses a ferroelectric capacitor, the magnetic RAM (MRAM) which uses a tunneling magneto-resistive (TMR) layer, the phase change RAM memory which uses one or more chalcogenide alloys, etc.
Phase change RAM memory, or PRAM, is a non-volatile memory device which uses a change in the phase (or state) of a material due to an applied temperature change to indicate a data state. Typically, the particular state of the phase-changeable material within a PRAM will be associated with an electrical resistance indicating a corresponding data state (e.g., a “1” or a “0” value). PRAM is relatively easy to fabricate and is therefore a cost effective approach to the implementation of a large capacity memory.
FIG. (FIG.) 1 is a diagram of a memory cell 10 of a phase change memory device. Referring to FIG. 1, the memory cell 10 is a metal-oxide semiconductor (MOS) switch type phase change memory cell, and includes a memory element 11 and a select element 12. The memory element 11 is connected between a bitline BL and the select element 12, and the select element 12 is connected between the memory element 11 and ground GND.
The memory cell 11 includes a phase change material, such as GST which is a conventionally understood material including germanium Ge, antimony Sb, and tellurium Te. GST is characterized by two stable states (i.e., a crystalline state and an amorphous state) that may be switched between by application of a appropriate temperature condition. Each of these two states has a distinct electrical resistance. The state of the GST may be defined by the application of corresponding temperature condition (i.e., a temperature level over a period of time). Such temperature conditions may be induced by application of an electric current supplied via the bitline BL. Once the phase of the GST is defined in this manner, the corresponding resistance of the memory cell (and its affect on an applied read current) may be interpreted (or detected) during read operations subsequently applied to the memory cell.
The select element 12 includes an n-type MOS (NMOS) transistor NT. A wordline WL is connected to the gate of the NMOS transistor NT. When an electric current is supplied to the wordline WL, the NMOS transistor is turned ON. When the NMOS transistor NT is turned ON, the memory element 11 receives an electric current via the bitline BL. In FIG. 1, the memory element 11 is connected between the bitline BL and the select element 12. However, the select element 12 may be connected between the bitline BL and the memory element 11.
FIG. 2 is a diagram of another memory cell 20 of a phase change memory device. Referring to FIG. 2, the memory cell 20 is a diode switch type phase change memory cell, and includes a memory element 21 and a select element 22. The memory element 21 is connected between a bitline BL and the select element 22, and the select element 22 is connected between the memory element 21 and a wordline WL. The memory element 21 is identical to the memory element 11 in FIG. 1.
The select element 22 includes a diode D. The memory element 21 is connected to the anode of the diode D, and a wordline WL is connected to the cathode of the diode D. When a difference between voltages of the anode and the cathode of the diode D is greater than the threshold voltage of the diode D, the diode D is turned on. When the diode D is turned on, the memory element 21 receives electric current via the bitline BL.
FIG. 3 is a graph describing the temperature condition characteristics of the GST shown in FIGS. 1 and 2. In FIG. 3, reference numeral 1 denotes a temperature condition used to place the GST in an amorphous state, and reference numeral 2 denotes an alternate temperature condition used to place the GST in a crystalline state.
Referring to FIG. 3, the GST enters an amorphous state when the GST is heated to a temperature higher than the melting temperature Tm of the GST by supplying an electric current over a first period of time T1, and then quickly quenching the GST. The amorphous state is generally referred as a reset state and a data value of ‘1’ is stored in the amorphous state. In contrast, the GST enters a crystalline state when the GST is heated to a temperature higher than the crystallization temperature Tc of the GST but lower than the Tm of the GST over a second period of time T2 longer than the first period of T1. The crystalline state is generally referred as a set state, and a data value of ‘0’ is stored in the crystalline state. Electrical resistance of a phase change memory cell varies with the amorphous volume of the GST. Thus, the electrical resistance of a phase change memory cell is relatively higher in an amorphous state and lower in a crystalline state.
A phase change memory device having the memory cell described in reference to FIGS. 1 through 3 generally discharges a corresponding bitline BL over defined period of time prior to an operation (e.g., a read or writing operation) in order to ensure proper execution of the operation. While bitline discharge is essential to the proper execution of the operation, the time required to do so is additive to the overall period of time necessary to perform a read or write operation. Therefore, the time required to discharge a bitline has the effect of extending read/write times and reducing the overall speed of operation for the memory device.